1. Field of the Invention
This invention relates to a semiconductor memory device using a silicon-on-insulator (SOI) device, and more particularly to a semiconductor memory device capable of reducing the topology between a cell region and a peripheral region and preventing floating body effect.
2. Description of the Related Art
The high integration of semiconductor devices such as DRAMs goes with reduction of a cell size and in this case, it is indispensable to increase the height of a capacitor so as to assure a desired capacitance. The capacitance is inversely proportional to the distance between capacitor electrodes which are a storage node and a plate node and proportional to a dimension of the capacitor electrode and a dielectric constant of a dielectric film. Therefore, reduction of the cell dimension causes the dimension of the capacitor electrode and so as to compensate this, it should be increase the height of the capacitor electrode. However, because the capacitor is formed only in a cell region, if the height of the capacitor is increased, the topology between the cell region and a peripheral region is largely increased. Accordingly, it is very difficult to form contact holes in the peripheral region in the following formation of metal interconnections.
On demand for a semiconductor memory device with high performance and low power, various studies on the semiconductor memory device and circuit have been progresses. In a device aspect, the semiconductor integration technology using a single crystal substrate being comprised of bulk Si is at the limit. Instead of the bulk silicon substrate, the semiconductor integration technology using the silicon on insulator (SOI) wafer is remarked, which includes a base substrate for supporting means, a buried oxide for bonding medium and a semiconductor layer for providing a device formation region in stack. It is because the devices fabricated in the SOI wafer have advantages of high performance due to reduction of capacitance, low driving voltage due to reduction of a threshold voltage and reduction in latch-up due to complete isolation, as compared with conventional devices fabricated in the silicon substrate.
As shown in FIG. 1, a body of a transistor 10 including a channel region 3a is floated from a base substrate 1 and holes generated by impact ionization in the transistor operation do not go out of the channel region 3a but remain in the channel region 3a. Because the SOI devices cause the floating body effect such as Kink phenomenon that the peak of the drain current in the transistor 10 rapidly rises, they do not utilize in general despite the above advantage. Accordingly, the memory device fabricated in the SOI wafer has an undesired characteristic in the circuit aspect, it is applicable to fabricate the semiconductor memory device with high performance and low power.
In FIG. 1, the reference numeral 2 designates a buried oxide, 3 a semiconductor layer, 4 an isolation film, 5 a gate oxide, a gate and 7 source/drain region, respectively.
Therefore, so as to fabricate the memory device with high performance and low power using the SOI wafer, it should solve the problem due to topology between the cell region and the peripheral region and the problem due to the floating body effect.
It is an object of the present invention to provide a semiconductor memory device with high performance and low power and a method for fabricating the same.
According to an aspect of the present invention, there is provided to a semiconductor memory device, comprising: a semiconductor layer including a cell region and a peripheral region; a first insulating layer formed over a lower surface of the semiconductor layer and having first and second contact holes exposing the semiconductor layer in the cell region and the semiconductor layer in the peripheral region, respectively; first isolation layers formed in the semiconductor layer of the cell region; second isolation layers formed in the semiconductor layer of the peripheral region to define a device formation region in the peripheral region; a pair of trench layers formed to define a device formation region in the semiconductor layer of the cell region and formed in the semiconductor layer between the first isolation layers to be spaced from the lower surface of the semiconductor layer; a cell transistor formed in the device formation region between the trench layers in the cell region, the cell transistor including a first gate having a first gate oxide formed over an upper surface of the semiconductor layer in the device formation region, first source and drain regions formed in the device formation region of the cell region at the both sides of the first gate and a channel region defined in the device formation region between the first source and drain regions; a driving transistor formed in the device formation region of the peripheral region, the driving transistor including a second gate having a second gate oxide formed over an upper surface of the semiconductor layer in the device formation region of the peripheral region, second source and drain regions formed in the device formation region of the peripheral region at the both sides of the second gate, and a channel region defined in the device formation region between the second source and drain regions; impurity regions for well pick-up formed in the upper surface of the semiconductor layer adjacent to the cell transistor; a capacitor formed over the first insulating layer in the cell region, the capacitor including a storage node formed over the first insulating layer to be contacted with the first source region of the cell transistor through the first contact hole and a dielectric film and a plate node formed over the storage node; a dummy pattern formed over the first insulating layer in the peripheral region, the dummy pattern including a first doped polysilicon layer, a second insulating layer and a second doped polysilicon layer formed over the first insulating layer of the peripheral region, the first doped polysilicon being contacted with the channel region of the driving transistor through the second contact hole; a third contact hole formed in the semiconductor layer and the first insulating layer in the peripheral region; a conduction layer formed within the third contact hole to be contacted with the first doped polysilicon layer of the dummy pattern; a third insulating layer formed over the plate node of the capacitor in the cell region and over the second doped polysilicon layer of the dummy pattern in the peripheral region; and a base substrate bonded on the third insulating layer.
There is also provided to a method for fabricating a semiconductor memory device, comprising the steps of: preparing a silicon substrate including a cell region and a peripheral region; in one surface of silicon substrate, forming first isolation layers in the cell region and second isolation layers in the peripheral region; forming a first insulating layer having first and second contact holes over the one surface of the silicon substrate including the first and second isolation layers; forming a first doped polysilicon layer over the first insulating layer to be buried with the first and second contact holes; patterning the first doped polysilicon layer to form a storage node of a capacitor in the cell region, the doped polysilicon layer remaining in the peripheral region as it is; forming a second insulating layer and a second doped polysilicon layer in turn over the first insulating layer including the storage node in the cell region and over the first doped polysilicon layer in the peripheral region; patterning the second insulating layer and the second doped polysilicon layer to form a dielectric film and a plate node of the capacitor, the second insulating layer and the second doped polysilicon layer remaining in the peripheral region as it is; forming a third insulating layer over the first insulating layer including the capacitor in the cell region and over the second doped polysilicon layer in the peripheral region; boding a base substrate on the third insulating layer; polishing another surface of the silicon substrate to form semiconductor layers in the cell region and the peripheral region, respectively, until the first and second isolation layers are exposed; forming a pair of trench layers in the semiconductor layer in the cell region to be spaced from the first insulating layer; forming a cell transistor in the semiconductor layer of the cell region between the trench layers and a driving transistor in the semiconductor layer of the peripheral region, the cell transistor including a first gate having a first gate oxide formed over the semiconductor layer in the cell region, first source and drain regions formed in the semiconductor layer of the cell region and a channel region defined in the semiconductor layer between the first source and drain regions in the cell region, the first source region of the cell transistor being contacted with the storage node of the capacitor, the driving transistor including a second gate having a second gate oxide formed over the semiconductor layer of the peripheral region, second source and drain regions formed in the semiconductor layer of the peripheral region and a channel region defined in the semiconductor layer between the second source and drain regions in the peripheral region, the channel region of the driving transistor being contacted with the first doped polysilicon layer of the dummy pattern; forming impurity regions for well pick-up in the another surface of the semiconductor layer in the cell region adjacent to the cell transistor; and forming a conduction layer in the semiconductor layer and the first insulating layer in the peripheral region adjacent to the driving transistor to be connected with the first doped polysilicon layer.